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[VHDL-FPGA-Verilog] random data gen（vhdl）

Description: 任意数据发生器的源代码-arbitrary data source code generator
Platform: | Size: 97280 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[VHDL-FPGA-Verilog] muxplusii --vhdl 经典程序

Description: 用VHDL编写的数字时钟,可变宽度脉冲产生器-prepared using VHDL digital clock, Variable width pulse generator, etc.
Platform: | Size: 8192 | Author: vhdp | Hits:

[VHDL-FPGA-Verilog] sin

Description: sin產生器，可以於VHDL產生sin之數值波形，進而輸出至dac做轉換-sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
Platform: | Size: 1084416 | Author: lin | Hits:

[SCM] digital_cymometer

Description: 简易数字频率计利用复杂可编程逻辑器件FPGA,VHDL编程将所有功能模块集成在一块芯片上。功能模块包括时基脉冲发生器、计数器、数据锁存器和显示电路4部分。设计时先分别设计各功能模块，并调试得到正确仿真结果，然后将各个功能模块组合起来。最后作整体仿真、下载，得到实物。由于采用纯数字硬件设计制作，稳定性、可靠性远远高于使用单片机或模拟方式实现的系统，外围电路简单。该数字频率计达到预期要求，实现了可变量程测量，测量范围0.1Hz—9999MHz，精度可达0.1Hz。-Simple digital frequency meter using complex programmable logic device FPGA, VHDL programming integration of all functional modules on a single chip. Functional modules, including time-base pulse generator, counters, and display data latch circuit 4. Design before the design of various functional modules, respectively, and debugging simulation results correctly, and then combine the various functional modules. Finally, for the overall simulation, download, be kind. As a result of the production of digital hardware design, stability, reliability is far higher than the use of single-chip microcomputer or analog means of the system, a simple peripheral circuits. The digital frequency meter to achieve the desired requirements of the variable-range measurement, measuring range 0.1Hz-9999MHz, accuracy up to 0.1Hz.
Platform: | Size: 412672 | Author: 严术骞 | Hits:

[VHDL-FPGA-Verilog] ntsc_gen

Description: NTSC信号发生器VHDL源码。输出为BT656格式-NTSC signal generator VHDL source code. BT656 format output
Platform: | Size: 1024 | Author: 吕奔 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] coreFFT_AR_3_0

Description: FFT算法VHDL生成器（Actel公司提供)-FFT algorithm for VHDL Generator (Actel offers)
Platform: | Size: 1406976 | Author: zhan | Hits:

[VHDL-FPGA-Verilog] multi-wave-creator

Description: 基于FPGA的多波形发生器（编程环境QuartusII6.0）-FPGA-based Multi-Waveform Generator (programming environment QuartusII6.0)
Platform: | Size: 1053696 | Author: 朱旋风 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: vhdl的一些源代码，包括dds 设计，交通灯设计，信号发生器设计的一些源代码-Some of VHDL source code, including dds design, traffic signal design, signal generator designed a number of source code
Platform: | Size: 70656 | Author: 马斌 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D159

Description: 正弦波发生器,VHDL的应用和处理,可以产生任意波形-Sine wave generator, VHDL applications and processing, can generate arbitrary waveform
Platform: | Size: 1731584 | Author: WBT | Hits:

[VHDL-FPGA-Verilog] vga_gen_46

Description: Verilog Vga Generator -Verilog Vga Generator
Platform: | Size: 1024 | Author: Fermat | Hits:

[VHDL-FPGA-Verilog] signal-generator

Description: FPGA 信号发生器的程序，在实验板上调试成功-FPGA signal generator procedures, the success of the experiment on-board debugging
Platform: | Size: 1024 | Author: 石头 | Hits:

[VHDL-FPGA-Verilog] epiano.vhdl

Description: 电子琴VHDL程序包含有：顶层程序、音阶发生器程序、数控分频模块程序和自动演奏模块程序-VHDL procedures flower contains: top-level procedures, scale generator procedures, numerical control frequency module procedures and module procedures performed automatically
Platform: | Size: 50176 | Author: 李立 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Platform: | Size: 2529280 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

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[VHDL-FPGA-Verilog] random data gen（vhdl）

[VHDL-FPGA-Verilog] 一些VHDL源代码

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

[VHDL-FPGA-Verilog] muxplusii --vhdl 经典程序

[VHDL-FPGA-Verilog] sin

[SCM] digital_cymometer

[VHDL-FPGA-Verilog] ntsc_gen

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] coreFFT_AR_3_0

[VHDL-FPGA-Verilog] multi-wave-creator

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] 61EDA_D159

[VHDL-FPGA-Verilog] vga_gen_46

[VHDL-FPGA-Verilog] signal-generator

[VHDL-FPGA-Verilog] epiano.vhdl

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] 1111

[VHDL-FPGA-Verilog] sinfasheng

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